1. Field of the Invention
The present invention generally relates to a semiconductor memory apparatus such as an SRAM, and more particularly, to a semiconductor memory apparatus of which memory space is accessible by a plurality of different addressing methods.
2. Description of the Related Art
FIG. 6 is a block diagram showing the internal structure of a random access memory (RAM) 100 as an example of conventional semiconductor memory apparatuses. The RAM 100 is configured so that its memory space is addressed using (mxc3x97n) wordsxc3x974 bits bit-slice type addressing method. FIG. 7 is a schematic diagram showing the three-dimensional memory space of the RAM showed in FIG. 6 in the case of m=n=4. FIG. 7 shows the case where Y=m (=4), X=n (=4), and Z=4.
When data are stored in the RAM 100, data items [A0, A1, A2, A3], [B0, B1, B2, B3], [C0, C1, C2, C3], AND [D0, D1, D2, D3], each having Z bits (=4, in this case) of data, are stored in respective addresses 0-3 as indicated on the top face of the memory space showed in FIG. 7. This addressing method is called xe2x80x9cbit slicexe2x80x9d type addressing.
In the following description, [A0, A1, A2, A3] will be written A[0:3], for example. Likewise, ADD[3:0] means [ADD3, ADD2, ADD1, ADD0], for example.
In the case of the conventional RAM 100, however, it is impossible to read the data as data items each having Y bits (=4, in this case) such as [A0, B0, C0, DO], [A1, B1, C1, D1], [A2, B2, C2, D2], and [A3, B3, C3, D3] using xe2x80x9cword slicexe2x80x9d type addressing.
If one uses four pieces of RAM 100 as a set as showed in FIG. 8, the user can read the data stored in the set of RAM 100 by the xe2x80x9cword slicexe2x80x9d type addressing method.
In FIG. 8, RAM 100a-100d has the same structure as the RAM 100 but it is assumed that m=n=2 in this case. An address control circuit 101 receives the following signals from a control circuit 102: address data ADD[3:0], a selection signal ZY-SEL indicating whether the data are to be accessed by the unit of Z bits or Y bits (that is, the bit slice type addressing or the word slice type addressing), and a chip enable signal CEB. The address control circuit 101 decodes the above signals and accesses RAM 100a-100d. 
When the control circuit 102 gives the address control circuit 101 an instruction to access the memory space by Z bits (bit slice addressing) through the selection signal ZY-SEL and gives each RAM 100a -100d an instruction to write data by a low level write enable signal WEB, data DO[3:0] (DO3-DO0) output by the control circuit 102 are stored in the RAM 100a-100d controlled by the address control circuit 101 depending on the address data ADD [1:0].
In the RAM 100a, data are written in addresses by Z bits, that is, each address indicated as 0, 4, 8, C showed on the top face of FIG. 7. Likewise, in the RAM 100b, data are written in each address indicated as 1, 5, 9, D showed on the top face of FIG. 7. In the RAM 100c, data are written in each address indicated as 2, 6, A, E showed on the top face of FIG. 7. In the RAM 100d, data are written in each address indicated as 3, 7, B, F showed on the top face of FIG. 7. Only data A[0:3], B[0:3], C[0:3], D[0:3] are showed in FIG. 8.
In the case where the control circuit 102 gives the address control circuit 101 an instruction to access data by Y bits (word slice addressing), and the control circuit 102 further gives each RAM 100a -100d an instruction to read data by a high level write enable signal, the data designated by the address control circuit 101 are output through each data output terminal DOUT[3:0].
The data output terminal DOUT[3:0] of each RAM 100a-100d is connected to corresponding multiplexer MUXa-MUXd. Each multiplexer MUXa-MUXd selectively outputs 1 bit of the data output through the data output terminal DOUT[3:0]. Data of 4 bits in total are input to the data input terminal DI[3:0] of the control circuit 102. A bit selection signal BITSEL[3:0] indicating the position in the 4-bit data output from each data output terminal DOUT[3:0] is sent from the address control circuit 101 to the multiplexer MUXa-MUXd. Accordingly, the memory storage circuit showed in FIG. 8 can read Y-bit data stored in the addresses A0, B0, C0, and D0.
However, this configuration includes four sets of circuits, each controlling the operation of each RAM 100a-100d, and requires the external multiplexers MUXa-MUXd, which results in a large circuit area.
The circuit configuration showed in FIG. 8 realizes data writing by Z-bit and data reading by Y-bit. If one desires data writing by Y-bit and data reading by Z-bit, data writing and data reading by Z-bit, or data reading and data writing by Y-bit, he/she needs to provide additional circuits such as registers. The additional circuits increase the circuit area as well as wiring area.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor memory apparatus in which one or more of the problems described above are eliminated.
Another and more specific object of the present invention is to provide a semiconductor memory apparatus of which data are accessible using different addressing types. A plurality of column gates are connected to the bit lines. Selection signals from an exterior designating which addressing type is to be used, bit slice type or word slice type, and column gate selection signals that are decoded address data from the exterior are input to each memory cell connected to the same word line. Accordingly, the semiconductor memory apparatus allows accessing data stored therein using different addressing types, and at the same time, the circuit area and the wiring region are reduced.
To achieve one or more of the above objects, a semiconductor memory apparatus according to the present invention, having a plurality of memory elements and a control circuit controlling each of the memory elements in response to control signals and address data input from an exterior, is characterized in that each of the memory elements includes a memory cell array in which a plurality of memory cells are arranged in a matrix with a plurality of pairs of bit lines on each column of the matrix and a plurality of word lines on each row of the matrix, each of the memory cells being connected to a corresponding pair of bit lines and corresponding one of the word lines, wherein a data signal is input to or output from the memory cells through the pair of bit lines and an enable signal is transferred to the corresponding memory cells through the corresponding one of the word lines, a first pair of data lines correspondingly provided to the memory cell array, a plurality of second pairs of data lines correspondingly provided to respective pairs of bit lines of the memory cell array, shared by the other memory elements, a plurality of column gates that connect, in response to a control signal from said control circuit, the corresponding pair of bit lines to the first pair of data lines or the corresponding one of the second pairs of data lines, a first sense amp that amplifies and outputs, when data are to be retrieved, in response to a control signal from the control circuit, the signal output through the first pair of data lines, a first write buffer that stores, when data are to be stored, in response to a control signal from the control circuit, the data in desired one of the memory cells through the first pair of data lines, a second sense amp that amplifies and outputs, when data are to be retrieved, in response to a control signal from the control circuit, the signal output through the second pair of data lines, a second write buffer that stores, when data are to be stored, in response to a control signal from the control circuit, the data in desired one of the memory cells through the second pair of data lines.
When accessing the memory cell array by Z bits, each column gate in the memory elements, in response to a control signal from the control circuit, connects the corresponding pair of bit lines to the enabled first sense amp and the enabled first write buffer through the first pair of data lines (bit slice type addressing by Z bits).
When accessing the memory cell array by Y bits, each column gate in the memory element, in response to a control signal from the control circuit, connects the corresponding pair of bit lines to the enabled second sense amp and the enabled second write buffer through the second pair of data lines (word slice type addressing by Y bits).
Other objects, features, and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.